The present invention generally relates to semiconductor structures, and more particularly to p-type field effect transistor (p-FET) devices having a graded silicon-germanium channel region, and a method for making the same.
Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Depending whether the on-state current is carried by electrons or holes, the FET comes as an n-FET device or a p-FET device. The overall fabrication process may include forming a gate structure over a channel region connecting source-drain regions within a semiconductor substrate on opposite sides of the gate, typically with some vertical overlap between the gate and the source-drain region.
An alternative for continued scaling of planar FETs to the 22 nm node and beyond may include the formation of CMOS devices on extremely thin semiconductor-on-insulator (ETSOI) substrates. ETSOI FETs are fully depleted metal-oxide semiconductor field effect transistor (MOSFET) devices having a thin channel region. Currently, fin field effect transistors (FinFETs) are becoming more widely used, primarily because they may offer better performance than planar FETs at the same power budget.
FinFETs are three dimensional (3-D), fully depleted MOSFET devices having a fin structure formed from the semiconductor substrate material. The fins may extend between the device source and drain surrounding a channel region forming the bulk of the semiconductor device. The gate structure may be located over the fins covering the channel region. FinFETs architecture may allow for a more precise control of the conducting channel by the gate, significantly reducing the amount of current leakage when the device is in off state.
Fully depleted MOSFETs having a silicon-germanium (SiGe) channel region may be considered an effective way to improve device performance. However, SiGe channel MOSFETs including FinFETs and ETSOI FETs, usually exhibit higher current leakage. Current leakage in SiGe channel MOSFETs may be attributed to the fact that devices including a silicon-germanium channel region may have a smaller band gap than devices including a silicon channel region.